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DTSTAMP:20250822T115809Z
LOCATION:Room 5.0A52
DTSTART;TZID=Europe/Stockholm:20250617T160000
DTEND;TZID=Europe/Stockholm:20250617T163000
UID:submissions.pasc-conference.org_PASC25_sess119_msa185@linklings.com
SUMMARY:Benchmarking and Co-Design at System and Processor Level
DESCRIPTION:Estela Suarez (Forschungszentrum Jülich, University of Bonn)\n
 \nBenchmarking provides insight into the behaviour of application codes an
 d their kernels on HPC systems. This is useful for identifying bottlenecks
  and performance tuning on the application side, as well as for understand
 ing how specific hardware features can impact (positively or negatively) t
 he performance of those applications. It is therefore natural to use bench
 marking as a vehicle for "co-design". Since this is also a term that finds
  different definitions, we would like to specify here that we refer to co-
 design in the sense of studying the interaction between application code, 
 system software, and hardware components in search of the modifications at
  each of these three levels that would bring the best overall performance 
 and energy efficiency. In this talk, we will present experiences on the us
 e of benchmarking for co-design purposes gathered in the EU-funded DEEP an
 d EPI projects. While in the former we looked at the system level, in the 
 latter the focus is on the processor and even core level. We will describe
  the differences between the two and the challenges that we found.\n\nDoma
 in: Engineering, Physics, Computational Methods and Applied Mathematics\n\
 nSession Chair: Olga Pearce (Lawrence Livermore National Laboratory, TAMU)
 \n\n
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